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- // Aplica o back-end do juninho
- @target : mips
- // Especifica o tipo de metodo empregado para salvar o resultado da compilação
- //@export : MultCoreJun
- @export : simulation
- package main;
- const (
- LIN = 2
- COL = 2
- )
- var (
- matrizA [LIN][COL]int32
- matrizB [LIN][COL]int32
- matrizR [LIN][COL]int32
- )
- func preenche(){
- var k = 1
- for i := 0; i < LIN ; i++ {
- for j := 0; j < COL ; j++ {
- matrizA[i][j] = k
- matrizB[i][j] = k
- k++
- }
- }
- }
- func multiplica() {
- var aux = 0
- for i := 0; i < LIN; i++ {
- for j := 0; j < COL; j++ {
- for k := 0; k < LIN; k++ {
- aux = aux + (matrizA[i][k] * matrizB[k][j])
- }
- matrizR[i][j] = aux
- aux = 0
- }
- }
- }
- func main() {
- preenche()
- multiplica()
- }
- /**
- alloc (int32), 4 _G13 T< alloc >
- alloc (int32), 4 _G18 T< alloc >
- alloc (int32), 4 _G54 T< alloc >
- <main>:
- 0: 0: call <preenche> T< call >
- 1: 1: call <multiplica> T< call >
- <main-end>:
- <preenche>:
- alloc (int32), 1 _VJ5 T< alloc >
- alloc (int32), 1 _VI3 T< alloc >
- alloc (int32), 1 _VK1 T< alloc >
- 2: 0: store (int32) _VK1, 1 T< store >
- 3: 1: store (int32) _VI3, 0 T< store >
- 4: 2: goto <preenche+_i3> T< jump >
- <preenche+_i0>:
- 5: 3: store (int32) _VJ5, 0 T< store >
- 6: 4: goto <preenche+_i7> T< jump >
- <preenche+_i4>:
- 7: 5: load (int32) _VI3, _S8 --Copy value of index T< load >
- 8: 6: _T9 := _S8 << 1 T< assign >
- 9: 7: load (int32) _VJ5, _S10 --Copy value of index T< load >
- 10: 8: _T9 := _T9 + _S10 --colls shift T< assign >
- 11: 9: _T12 := _T9 << 2 T< assign >
- 12: 10: load (int32) _VK1, _S7 --Load param (_S7) T< load >
- 13: 11: store (int32) _G13[_T12], _S7 T< store >
- 14: 12: _S8 := _S8 --Copy value of index T< copy >
- 15: 13: store (int32) _VI3, _S8 T< store >
- 16: 14: _T15 := _S8 << 1 T< assign >
- 17: 15: _S10 := _S10 --Copy value of index T< copy >
- 18: 16: store (int32) _VJ5, _S10 T< store >
- 19: 17: _T15 := _T15 + _S10 --colls shift T< assign >
- 20: 18: _T17 := _T15 << 2 T< assign >
- 21: 19: store (int32) _G18[_T17], _S7 T< store >
- 22: 20: _S7 := _S7 + 1 T< assign >
- 23: 21: store (int32) _VK1, _S7 T< store >
- 24: 22: _S10 := _S10 + 1 T< assign >
- 25: 23: store (int32) _VJ5, _S10 T< store >
- <preenche+_i7>:
- 26: 24: load (int32) _VJ5, _S20 --Load param (_S20) T< load >
- 27: 25: if _S20 < 2 goto <preenche+_i4> T< branch >
- 28: 26: load (int32) _VI3, _S21 --Load param (_S21) T< load >
- 29: 27: _S21 := _S21 + 1 T< assign >
- 30: 28: store (int32) _VI3, _S21 T< store >
- <preenche+_i3>:
- 31: 29: load (int32) _VI3, _S22 --Load param (_S22) T< load >
- 32: 30: if _S22 < 2 goto <preenche+_i0> T< branch >
- <preenche-end>:
- <multiplica>:
- alloc (int32), 1 _VK29 T< alloc >
- alloc (int32), 1 _VJ27 T< alloc >
- alloc (int32), 1 _VI25 T< alloc >
- alloc (int32), 1 _VAUX23 T< alloc >
- 33: 0: store (int32) _VAUX23, 0 T< store >
- 34: 1: store (int32) _VI25, 0 T< store >
- 35: 2: goto <multiplica+_i11> T< jump >
- <multiplica+_i8>:
- 36: 3: store (int32) _VJ27, 0 T< store >
- 37: 4: goto <multiplica+_i15> T< jump >
- <multiplica+_i12>:
- 38: 5: store (int32) _VK29, 0 T< store >
- 39: 6: goto <multiplica+_i19> T< jump >
- <multiplica+_i16>:
- 40: 7: load (int32) _VI25, _S32 --Copy value of index T< load >
- 41: 8: _T33 := _S32 << 1 T< assign >
- 42: 9: load (int32) _VK29, _S34 --Copy value of index T< load >
- 43: 10: _T33 := _T33 + _S34 --colls shift T< assign >
- 44: 11: _T36 := _T33 << 2 T< assign >
- 45: 12: load (int32) _G13[_T36], _T38 T< load >
- 46: 13: _S34 := _S34 --Copy value of index T< copy >
- 47: 14: store (int32) _VK29, _S34 T< store >
- 48: 15: _T39 := _S34 << 1 T< assign >
- 49: 16: load (int32) _VJ27, _S40 --Copy value of index T< load >
- 50: 17: _T39 := _T39 + _S40 --colls shift T< assign >
- 51: 18: _T42 := _T39 << 2 T< assign >
- 52: 19: load (int32) _G18[_T42], _T44 T< load >
- 53: 20: _T45 := _T38 * _T44 T< assign >
- 54: 21: load (int32) _VAUX23, _S31 --Load param (_S31) T< load >
- 55: 22: _T46 := _S31 + _T45 T< assign >
- 56: 23: store (int32) _VAUX23, _T46 T< store >
- 57: 24: _S34 := _S34 + 1 T< assign >
- 58: 25: store (int32) _VK29, _S34 T< store >
- <multiplica+_i19>:
- 59: 26: load (int32) _VK29, _S47 --Load param (_S47) T< load >
- 60: 27: if _S47 < 2 goto <multiplica+_i16> T< branch >
- 61: 28: load (int32) _VI25, _S49 --Copy value of index T< load >
- 62: 29: _T50 := _S49 << 1 T< assign >
- 63: 30: load (int32) _VJ27, _S51 --Copy value of index T< load >
- 64: 31: _T50 := _T50 + _S51 --colls shift T< assign >
- 65: 32: _T53 := _T50 << 2 T< assign >
- 66: 33: load (int32) _VAUX23, _S48 --Load param (_S48) T< load >
- 67: 34: store (int32) _G54[_T53], _S48 T< store >
- 68: 35: store (int32) _VAUX23, 0 T< store >
- 69: 36: _S51 := _S51 + 1 T< assign >
- 70: 37: store (int32) _VJ27, _S51 T< store >
- <multiplica+_i15>:
- 71: 38: load (int32) _VJ27, _S56 --Load param (_S56) T< load >
- 72: 39: if _S56 < 2 goto <multiplica+_i12> T< branch >
- 73: 40: load (int32) _VI25, _S57 --Load param (_S57) T< load >
- 74: 41: _S57 := _S57 + 1 T< assign >
- 75: 42: store (int32) _VI25, _S57 T< store >
- <multiplica+_i11>:
- 76: 43: load (int32) _VI25, _S58 --Load param (_S58) T< load >
- 77: 44: if _S58 < 2 goto <multiplica+_i8> T< branch >
- <multiplica-end>:
- ec: 0666763248 addiu sp,sp,-16 -- prolog| push stack frame
- f0: 0001962017 addu fp,zero,sp -- prolog|copy fp ← sp
- f4: 2948595712 sw zero,0(fp) .0 -- store content of zero in _VAUX23
- f8: 2948595716 sw zero,4(fp) .1 -- store content of zero in _VI25
- fc: 0134217855 j 1fc <multiplica+0x110> .2 -- jump to multiplica+_i11
- 100: 0000000000 sll zero,zero,0 .2 -- Nop
- 104: 2948595720 sw zero,8(fp) .3 -- store content of zero in _VJ27
- 108: 0134217844 j 1d0 <multiplica+0xe4> .4 -- jump to multiplica+_i15
- 10c: 0000000000 sll zero,zero,0 .4 -- Nop
- 110: 2948595724 sw zero,12(fp) .5 -- store content of zero in _VK29
- 114: 0134217824 j 180 <multiplica+0x94> .6 -- jump to multiplica+_i19
- 118: 0000000000 sll zero,zero,0 .6 -- Nop
- 11c: 2413101060 lw s5,4(fp) .7 -- load content from _VI25 in s5
- 120: 0000000000 sll zero,zero,0 .7 -- Nop
- 124: 0001400896 sll t4,s5,1 .8 -- _T33 = _S32 << 1
- 128: 2413232140 lw s7,12(fp) .9 -- load content from _VK29 in s7
- 12c: 0000000000 sll zero,zero,0 .9 -- Nop
- 130: 0026697761 addu t4,t4,s7 .10 -- _T33 = _T33 + _S34
- 134: 0000813184 sll t5,t4,2 .11 -- _T36 = _T33 << 2
- 138: 2377580544 lw s7,0(t5) .12 -- load content from _G13[_T36] in t6
- 13c: 2950103052 sw s7,12(fp) .14 -- store content of s7 in _VK29
- 140: 0001538112 sll t7,s7,1 .15 -- _T39 = _S34 << 1
- 144: 2412904456 lw s2,8(fp) .16 -- load content from _VJ27 in s2
- 148: 0000000000 sll zero,zero,0 .16 -- Nop
- 14c: 0032667681 addu t7,t7,s2 .17 -- _T39 = _T39 + _S40
- 150: 0001032320 sll t8,t7,2 .18 -- _T42 = _T39 << 2
- 154: 2399666192 lw t0,16(t8) .19 -- load content from _G18[_T42] in t0
- 158: 0000000000 sll zero,zero,0 .19 -- Nop
- 15c: 0029902872 mult t6,t0 .20 -- _T45 = _T38 * _T44
- 160: 0000018450 mflo t1 .20
- 164: 2413101056 lw s5,0(fp) .21 -- load content from _VAUX23 in s5
- 168: 0000000000 sll zero,zero,0 .21 -- Nop
- 16c: 0044650529 addu t2,s5,t1 .22 -- _T46 = _S31 + _T45
- 170: 2949251072 sw t2,0(fp) .23 -- store content of t2 in _VAUX23
- 174: 0604700673 addiu t3,zero,1 .24 -- load param (p2)
- 178: 0653721601 addiu s7,s7,1 .24 -- _S34 = _S34 + 1
- 17c: 2950103052 sw s7,12(fp) .25 -- store content of s7 in _VK29
- 180: 2412838924 lw s1,12(fp) .26 -- load content from _VK29 in s1
- 184: 0000000000 sll zero,zero,0 .26 -- Nop
- 188: 0604766210 addiu t4,zero,2 .27 -- load param (p2)
- 18c: 0036442147 subu v0,s1,t4 .27
- 190: 0071368674 bltz v0,11c <multiplica+0x30> .27 -- branch if register < 0
- 194: 0000000000 sll zero,zero,0 .27 -- Nop
- 198: 2412969988 lw s3,4(fp) .28 -- load content from _VI25 in s3
- 19c: 0000000000 sll zero,zero,0 .28 -- Nop
- 1a0: 0001271872 sll t5,s3,1 .29 -- _T50 = _S49 << 1
- 1a4: 2413035528 lw s4,8(fp) .30 -- load content from _VJ27 in s4
- 1a8: 0000000000 sll zero,zero,0 .30 -- Nop
- 1ac: 0028600353 addu t5,t5,s4 .31 -- _T50 = _T50 + _S51
- 1b0: 0000882816 sll t7,t5,2 .32 -- _T53 = _T50 << 2
- 1b4: 2413166592 lw s6,0(fp) .33 -- load content from _VAUX23 in s6
- 1b8: 0000000000 sll zero,zero,0 .33 -- Nop
- 1bc: 2918580256 sw s6,32(t7) .34 -- store content of s6 in _G54[_T53]
- 1c0: 2948595712 sw zero,0(fp) .35 -- store content of zero in _VAUX23
- 1c4: 0604897281 addiu t6,zero,1 .36 -- load param (p2)
- 1c8: 0647233537 addiu s4,s4,1 .36 -- _S51 = _S51 + 1
- 1cc: 2949906440 sw s4,8(fp) .37 -- store content of s4 in _VJ27
- 1d0: 2412904456 lw s2,8(fp) .38 -- load content from _VJ27 in s2
- 1d4: 0000000000 sll zero,zero,0 .38 -- Nop
- 1d8: 0604504066 addiu t0,zero,2 .39 -- load param (p2)
- 1dc: 0038277155 subu v0,s2,t0 .39
- 1e0: 0071368651 bltz v0,110 <multiplica+0x24> .39 -- branch if register < 0
- 1e4: 0000000000 sll zero,zero,0 .39 -- Nop
- 1e8: 2413166596 lw s6,4(fp) .40 -- load content from _VI25 in s6
- 1ec: 0000000000 sll zero,zero,0 .40 -- Nop
- 1f0: 0604569601 addiu t1,zero,1 .41 -- load param (p2)
- 1f4: 0651558913 addiu s6,s6,1 .41 -- _S57 = _S57 + 1
- 1f8: 2950037508 sw s6,4(fp) .42 -- store content of s6 in _VI25
- 1fc: 2413232132 lw s7,4(fp) .43 -- load content from _VI25 in s7
- 200: 0000000000 sll zero,zero,0 .43 -- Nop
- 204: 0604635138 addiu t2,zero,2 .44 -- load param (p2)
- 208: 0048893987 subu v0,s7,t2 .44
- 20c: 0071368637 bltz v0,104 <multiplica+0x18> .44 -- branch if register < 0
- 210: 0000000000 sll zero,zero,0 .44 -- Nop
- 214: 0666697744 addiu sp,sp,16 -- epilog| pop stack frame
- 218: 0001962017 addu fp,zero,sp -- epilog| pop stack frame
- 21c: 0065011720 jr ra -- epilog| return
- */
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