ivannosys3/src/samples/program_jun_laplaciano.go

// Aplica o back-end do juninho
@target          : mips 
// Especifica o tipo de metodo empregado para salvar o resultado da compilação
@export          : simulation //MultCoreJun

// Diretorio onde o resultado da compilação será gravado
@outputDirectory : `C:\Users\EUGENIO CARVALHO\Desktop\tmp\laplaciano`

// Quantidade de palavras de um bloco 32 palavras de 4bytes
@cacheBlockSize: `32`

/**
    Profile de compilacao do back-end
    O formato da string é um json que descreve um array de definições de cada core
    {
        "stackBaseAddress"   : 5888,     -> endereço da base da pilha do core em questão
        "initFunction": "multiplica(0)", -> define a main de cada core. aceita ate 4 parametros com valores de constantes
        "id": "core0"                    -> label que define o codigo de cada core
    },

    Se "stackBaseAddress" não for definido o compilador irá inferir o valor iniciando do ultimo endereço da memoria    
*/

@profile: `[
    {
        "id"               : "core0",
        "initFunction"     : "multiplica(0)",
        "filename"         : "%s_core_0.txt"
    },
    {
        "id"               : "core1",
        "initFunction"     : "multiplica(5)",
        "filename"         : "%s_core_1.txt"
    },
    {
        "id"               : "core2",
        "initFunction"     : "multiplica(10)",
        "filename"         : "%s_core_2.txt"
    },
    {
        "id"               : "core3",
        "initFunction"     : "multiplica(15)",
        "filename"         : "%s_core_3.txt"
    }
]`


package main;

const (
    LIN = 4
    COL = 4
)

var (
    origin [LIN][COL]int32
    result [LIN][COL]int32
)

func preenche_matriz() {
    var (
        w = 1
        value int32
    )
    
    LM1 := LIN - 1
    CM1 := COL - 1

    for i := 0; i < LIN; i++ {
        for j := 0; j < COL; j++ {
            switch {
                case i == 0, i == LM1: // Primeira  e ultima linha
                    value = 0
                case j == 0, j == CM1: // Primeira e ultima coluna
                    value = 0
                default:               // Elementos do interior da matriz
                    value = w
                    w++
            }
            origin[i][j] = value
        }
    }
}

func laplaciano() {
    var (
        l int32
    )
    LM1 := LIN - 1
    CM1 := COL - 1

    for i:= 1; i < LM1; i++ {
        for j := 1; j < CM1; j++ {
            l = origin[i-1][j]
            l += origin[i][j-1] 
            l += origin[i][j+1] 
            l += origin[i+1][j] 
            l -= (4 * origin[i][j])

            if l > 255 { l = 255 }

            result[i][j] = l
        }
    }
}

func main() {
    preenche_matriz()
    laplaciano()
}

/**
main.@preenche_matriz.main.@preenche_matriz.value : _V8
main.@preenche_matriz.@for_0.main.@preenche_matriz.@for_0.i : _V6
main.@preenche_matriz.@for_0.@for_1.COL : 4
main.@preenche_matriz.main.@preenche_matriz.LM1 : _V3
main.@preenche_matriz.@for_0.@for_1.LM1 : _V3
main.main.result : _G90
main.@preenche_matriz.w : _V1
main.@preenche_matriz.@for_0.@for_1.main.@preenche_matriz.@for_0.@for_1.j : _V7
main.@preenche_matriz.@for_0.@for_1.CM1 : _V5
main.@preenche_matriz.@for_0.@for_1.value : _V8
main.@preenche_matriz.@for_0.LIN : 4
_V1 : main.@preenche_matriz.w
_V3 : main.@preenche_matriz.LM1
_V6 : main.@preenche_matriz.@for_0.i
_V5 : main.@preenche_matriz.CM1
main.@preenche_matriz.@for_0.i : _V6
_V8 : main.@preenche_matriz.@for_0.@for_1.value
_V7 : main.@preenche_matriz.@for_0.@for_1.j
_G18 : main.main.origin
main.@preenche_matriz.@for_0.@for_1.i : _V6
main.@preenche_matriz.CM1 : _V5
main.@preenche_matriz.LIN : 4
main.@preenche_matriz.main.@preenche_matriz.CM1 : _V5
main.@preenche_matriz.COL : 4
main.@preenche_matriz.main.@preenche_matriz.w : _V1
main.@preenche_matriz.@for_0.@for_1.origin : _G18
main.main.origin : _G18
_G90 : main.main.result
main.@preenche_matriz.@for_0.@for_1.w : _V1
main.@preenche_matriz.LM1 : _V3
main.@preenche_matriz.@for_0.@for_1.j : _V7



4 : main.@laplaciano.LIN
main.@laplaciano.LIN : 4

main.@laplaciano.COL : 4

_V22 : main.@laplaciano.CM1
main.@laplaciano.CM1 : _V22
main.@laplaciano.main.@laplaciano.CM1 : _V22
main.@laplaciano.@for_3.@for_4.CM1 : _V22

_V20 : main.@laplaciano.LM1
main.@laplaciano.LM1 : _V20
main.@laplaciano.@for_3.LM1 : _V20
main.@laplaciano.main.@laplaciano.LM1 : _V20

main.@laplaciano.@for_3.i : _V23
_V23 : main.@laplaciano.@for_3.i
main.@laplaciano.@for_3.@for_4.i : _V23
main.@laplaciano.@for_3.main.@laplaciano.@for_3.i : _V23

main.@laplaciano.main.@laplaciano.l : _V36
main.@laplaciano.@for_3.@for_4.l : _V36
_V36 : main.@laplaciano.@for_3.@for_4.l

_V24 : main.@laplaciano.@for_3.@for_4.j
main.@laplaciano.@for_3.@for_4.j : _V24
main.@laplaciano.@for_3.@for_4.main.@laplaciano.@for_3.@for_4.j : _V24

main.@laplaciano.@for_3.@for_4.origin : _G18
main.@laplaciano.@for_3.@for_4.result : _G90


		<laplaciano>:
16c:  0666763244	addiu sp,sp,-20		 -- prolog| push stack frame
170:  0001962017	addu fp,zero,sp		 -- prolog|copy fp ← sp
174:  0605028355	addiu s0,zero,3		.0 -- copy _V20 ← 3
178:  2949644288	sw s0,fp,0		.1 -- store content of s0 in _V20
17c:  0605093891	addiu s1,zero,3		.2 -- copy _V22 ← 3
180:  2949709828	sw s1,fp,4		.3 -- store content of s1 in _V22
184:  0605159425	addiu s2,zero,1		.4 -- copy _V23 ← 1
188:  2949775368	sw s2,fp,8		.5 -- store content of s2 in _V23
18c:  0134217947	j 36c <laplaciano+0x200>		.6 -- jump to laplaciano+_i20
190:  0000000000	sll zero,zero,0		.6 -- Nop
194:  0605224961	addiu s3,zero,1		.7 -- copy _V24 ← 1
198:  2949840908	sw s3,fp,12		.8 -- store content of s3 in _V24
19c:  0134217937	j 344 <laplaciano+0x1d8>		.9 -- jump to laplaciano+_i24
1a0:  0000000000	sll zero,zero,0		.9 -- Nop
1a4:  2413035528	lw s4,fp,8		.10 -- load content from _V23 in s4
1a8:  0000000000	sll zero,zero,0		.10 -- Nop
1ac:  0646840319	addiu t5,s4,-1		.11 -- _T26 = _V23 - 1
1b0:  0000880768	sll t6,t5,2		.12 -- _T27 = _T26 << 2
1b4:  2413101068	lw s5,fp,12		.13 -- load content from _V24 in s5
1b8:  0000000000	sll zero,zero,0		.13 -- Nop
1bc:  0001407009	addu t7,zero,s5		.14 -- copy _T29 ← _V24
1c0:  0030371873	addu t6,t6,t7		.15 -- _T27 = _T27 + _T29
1c4:  0000966784	sll t8,t6,2		.16 -- _T33 = _T27 << 2
1c8:  0060342305	addu t8,gp,t8		.17
1cc:  2400583680	lw s6,t8,0		.17
1d0:  0000000000	sll zero,zero,0		.17 -- Nop
1d4:  0001488929	addu s7,zero,s6		.17 -- copy s7 ← s6
1d8:  2950103056	sw s7,fp,16		.18 -- store content of s7 in _V36
1dc:  2413035528	lw s4,fp,8		.19 -- load content from _V23 in s4
1e0:  0000000000	sll zero,zero,0		.19 -- Nop
1e4:  0001327137	addu t0,zero,s4		.20 -- copy _T37 ← _V23
1e8:  0000542848	sll t1,t0,2		.21 -- _T38 = _T37 << 2
1ec:  2413101068	lw s5,fp,12		.22 -- load content from _V24 in s5
1f0:  0000000000	sll zero,zero,0		.22 -- Nop
1f4:  0648806399	addiu t3,s5,-1		.23 -- _T41 = _V24 - 1
1f8:  0019613729	addu t1,t1,t3		.24 -- _T38 = _T38 + _T41
1fc:  0000614528	sll t4,t1,2		.25 -- _T45 = _T38 << 2
200:  0059531297	addu t4,gp,t4		.26
204:  2374828032	lw t5,t4,0		.26
208:  2413232144	lw s7,fp,16		.27 -- load content from _V36 in s7
20c:  0000000000	sll zero,zero,0		.27 -- Nop
210:  0049133601	addu s7,s7,t5		.28 -- _V36 = _V36 + _T47
214:  2950103056	sw s7,fp,16		.29 -- store content of s7 in _V36
218:  2413035528	lw s4,fp,8		.30 -- load content from _V23 in s4
21c:  0000000000	sll zero,zero,0		.30 -- Nop
220:  0001341473	addu t7,zero,s4		.31 -- copy _T48 ← _V23
224:  0001011840	sll t6,t7,2		.32 -- _T49 = _T48 << 2
228:  2413101068	lw s5,fp,12		.33 -- load content from _V24 in s5
22c:  0000000000	sll zero,zero,0		.33 -- Nop
230:  0648544257	addiu t0,s5,1		.34 -- _T52 = _V24 + 1
234:  0029913121	addu t6,t6,t0		.35 -- _T49 = _T49 + _T52
238:  0000938112	sll t2,t6,2		.36 -- _T56 = _T49 << 2
23c:  0059396129	addu t2,gp,t2		.37
240:  2370502656	lw t3,t2,0		.37
244:  2413232144	lw s7,fp,16		.38 -- load content from _V36 in s7
248:  0000000000	sll zero,zero,0		.38 -- Nop
24c:  0049002529	addu s7,s7,t3		.39 -- _V36 = _V36 + _T58
250:  2950103056	sw s7,fp,16		.40 -- store content of s7 in _V36
254:  2413035528	lw s4,fp,8		.41 -- load content from _V23 in s4
258:  0000000000	sll zero,zero,0		.41 -- Nop
25c:  0646709249	addiu t4,s4,1		.42 -- _T60 = _V23 + 1
260:  0000813184	sll t5,t4,2		.43 -- _T61 = _T60 << 2
264:  2413101068	lw s5,fp,12		.44 -- load content from _V24 in s5
268:  0000000000	sll zero,zero,0		.44 -- Nop
26c:  0001407009	addu t7,zero,s5		.45 -- copy _T63 ← _V24
270:  0028272673	addu t5,t5,t7		.46 -- _T61 = _T61 + _T63
274:  0000901248	sll t8,t5,2		.47 -- _T67 = _T61 << 2
278:  0060342305	addu t8,gp,t8		.48
27c:  2399666176	lw t0,t8,0		.48
280:  2413232144	lw s7,fp,16		.49 -- load content from _V36 in s7
284:  0000000000	sll zero,zero,0		.49 -- Nop
288:  0048805921	addu s7,s7,t0		.50 -- _V36 = _V36 + _T69
28c:  2950103056	sw s7,fp,16		.51 -- store content of s7 in _V36
290:  2413035528	lw s4,fp,8		.52 -- load content from _V23 in s4
294:  0000000000	sll zero,zero,0		.52 -- Nop
298:  0001339425	addu t6,zero,s4		.53 -- copy _T70 ← _V23
29c:  0000938112	sll t2,t6,2		.54 -- _T71 = _T70 << 2
2a0:  2413101068	lw s5,fp,12		.55 -- load content from _V24 in s5
2a4:  0000000000	sll zero,zero,0		.55 -- Nop
2a8:  0001398817	addu t3,zero,s5		.56 -- copy _T73 ← _V24
2ac:  0021712929	addu t2,t2,t3		.57 -- _T71 = _T71 + _T73
2b0:  0000673920	sll t1,t2,2		.58 -- _T77 = _T71 << 2
2b4:  0059328545	addu t1,gp,t1		.59
2b8:  2368929792	lw s3,t1,0		.59
2bc:  0000000000	sll zero,zero,0		.59 -- Nop
2c0:  0001269793	addu t4,zero,s3		.59 -- copy t4 ← s3
2c4:  0604962820	addiu t7,zero,4		.60
2c8:  0026175512	mult t4,t7		.60 -- _T80 = _T79 * 4
2cc:  0000026642	mflo t5		.60
2d0:  2413232144	lw s7,fp,16		.61 -- load content from _V36 in s7
2d4:  0000000000	sll zero,zero,0		.61 -- Nop
2d8:  0049133603	subu s7,s7,t5		.62 -- _V36 = _V36 - _T80
2dc:  2950103056	sw s7,fp,16		.63 -- store content of s7 in _V36
2e0:  2413232144	lw s7,fp,16		.64 -- load content from _V36 in s7
2e4:  0000000000	sll zero,zero,0		.64 -- Nop
2e8:  0605552895	addiu t8,zero,255		.65
2ec:  0049811491	subu v0,s7,t8		.65
2f0:  0406847491	blez v0,300 <laplaciano+0x194>		.65 -- branch if register <= 0
2f4:  0000000000	sll zero,zero,0		.65 -- Nop
2f8:  0605421823	addiu s6,zero,255		.66 -- copy _V36 ← 255
2fc:  2950037520	sw s6,fp,16		.67 -- store content of s6 in _V36
300:  2412773384	lw s0,fp,8		.68 -- load content from _V23 in s0
304:  0000000000	sll zero,zero,0		.68 -- Nop
308:  0001077281	addu t6,zero,s0		.69 -- copy _T81 ← _V23
30c:  0000940160	sll t3,t6,2		.70 -- _T82 = _T81 << 2
310:  2412838924	lw s1,fp,12		.71 -- load content from _V24 in s1
314:  0000000000	sll zero,zero,0		.71 -- Nop
318:  0001134625	addu t2,zero,s1		.72 -- copy _T84 ← _V24
31c:  0023746593	addu t3,t3,t2		.73 -- _T82 = _T82 + _T84
320:  0000739456	sll t1,t3,2		.74 -- _T88 = _T82 << 2
324:  2412904464	lw s2,fp,16		.75 -- load content from _V36 in s2
328:  0000000000	sll zero,zero,0		.75 -- Nop
32c:  0059328545	addu t1,gp,t1		.76
330:  2905735232	sw s2,t1,64		.76 -- store content of t1 in _G90[_T88]
334:  2413101068	lw s5,fp,12		.77 -- load content from _V24 in s5
338:  0000000000	sll zero,zero,0		.77 -- Nop
33c:  0649396225	addiu s5,s5,1		.78 -- _V24 = _V24 + 1
340:  2949971980	sw s5,fp,12		.79 -- store content of s5 in _V24
344:  2412969996	lw s3,fp,12		.80 -- load content from _V24 in s3
348:  2413232132	lw s7,fp,4		.81 -- load content from _V22 in s7
34c:  0000000000	sll zero,zero,0		.81 -- Nop
350:  0041357347	subu v0,s3,s7		.82
354:  0071368595	bltz v0,1a4 <laplaciano+0x38>		.82 -- branch if register < 0
358:  0000000000	sll zero,zero,0		.82 -- Nop
35c:  2413166600	lw s6,fp,8		.83 -- load content from _V23 in s6
360:  0000000000	sll zero,zero,0		.83 -- Nop
364:  0651558913	addiu s6,s6,1		.84 -- _V23 = _V23 + 1
368:  2950037512	sw s6,fp,8		.85 -- store content of s6 in _V23
36c:  2412773384	lw s0,fp,8		.86 -- load content from _V23 in s0
370:  2412838912	lw s1,fp,0		.87 -- load content from _V20 in s1
374:  0000000000	sll zero,zero,0		.87 -- Nop
378:  0034672675	subu v0,s0,s1		.88
37c:  0071368581	bltz v0,194 <laplaciano+0x28>		.88 -- branch if register < 0
380:  0000000000	sll zero,zero,0		.88 -- Nop
384:  0666697748	addiu sp,sp,20		 -- epilog| pop stack frame
388:  0001962017	addu fp,zero,sp		 -- epilog| pop stack frame
38c:  0065011720	jr ra		 -- epilog| return

*/